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A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA using Chisel HCL
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Amazon.com: Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware (Chapman & Hall/CRC Computer and Information Science Series): 9781584887416: Ou, Jingzhao, Prasanna, Viktor K.: Books
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A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA using Chisel HCL
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Energy-Efficient Design of Advanced Machine Learning Hardware | SpringerLink
Case Study: Robust Hardware, Application-Focused Software and AI Deliver Energy Savings for Smart Buildings - Sfera Labs
A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA using Chisel HCL
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PDF) Hardware and Software Solutions for Energy-Efficient Computing in Scientific Programming
